For example, a driving device for use in a power device such as a resonant converter or motor driver, comprises as shown in FIG. 6, a DC power source 3, first and second MOS-FETs 1 and 2 connected to DC power source 3 to be alternately turned on and off; an electric load 4 connected between a junction 6 of first and second MOS-FETs 1 and 2 and DC power source 3; a first control circuit 5 connected to a control or gate terminal of first MOS-FET 1; and a second control circuit 50 connected to a control or gate terminal of second MOS-FET 2 to form a half-bridge circuit in conjunction therewith. First control circuit 5 comprises a control DC power source 10; a first series circuit 11 which includes a first resistor 13 and a first control MOS-FET 8 connected in series to control DC power source 10; a second series circuit 12 which includes a second resistor 14 and a second control MOS-FET 9 connected in parallel to first series circuit 11 and in series to control DC power source 10; a drive signal generator 7 for forwarding drive signals to control or gate terminals of first and second control MOS-FETs 8 and 9; and a drive circuit 30 for forwarding drive signals to a control or gate terminal of first MOS-FET 1. Drive circuit 30 provides drive signals for a control or gate terminal of first MOS-FET 1 based on potentials on first and second series circuits 11 and 12. Control DC power source 10 has a positive terminal connected to first and second series circuits 11 and 12, and a negative terminal connected to a junction 6 of first and second MOS-FETs 1 and 2. Other kind of FETs such as junction field-effect transistors (J-FET) or insulated gate bipolar transistors (IGBT) may be used as first and second MOS-FETs 1 and 2 and first and second control MOS-FETs 8 and 9.
This half-bridge circuit has a trouble because reference potential of first MOS-FET 1 as a high voltage side may fluctuate between ground potential and input voltage Vin from DC power source 3 due to the on-off operation of first and second MOS-FETs 1 and 2, and to avoid such fluctuation in reference voltage, first MOS-FET 1 is driven by first control circuit 5 which involves a level shift circuit generally shown in FIG. 6. FIG. 7 indicates a time chart of voltages at selected junctions in the driving device shown in FIG. 6 wherein a junction A denotes a low potential for input voltage Vin from DC power source 3, and a junction B denotes a low potential for input voltage Vcc from control DC power source 10.
Drive circuit 30 comprises for example an RS flip flop (RSF/F) 31 and a well-known driver (not shown) connected between RSF/F 31 and gate terminal of first MOS-FET 1. RSF/F 31 has a set input terminal S connected to a junction 36 between a first resistor 13 and a first control MOS-FET 8 through a first low pass filter 34 and a reset input terminal R connected to a junction 37 of a second resistor 14 and second control MOS-FET 9 through a second low pass filter 35. FIGS. 7 C and F indicate a threshold value as Vth of low pass filter circuits 34 and 35.
Second MOS-FET 2 of low voltage side is driven by second control circuit 50, a well-known driver. After second MOS-FET 2 is turned off as shown in FIG. 7 A, a dead time starts to provide the simultaneous off-period for both first and second MOS-FETs 1 and 2, and thereby certainly prevent the simultaneous on-period or attain zero voltage switching (ZVS) thereof. After the time course of the simultaneous off-period, drive signal generator 7, a well-known pulse generator produces a set signal to gate signal of first control MOS-FET 8 which therefore is turned on to cause electric current to flow from control DC power source 10 through first resistor 13 and first control MOS-FET 8. At this time, a signal of low voltage at junction 36 is applied through first low pass filter 34 on set input terminal S of RSF/F 31 which therefore produces at output terminal Q an output of high voltage level to gate terminal of first MOS-FET 1 to turn it on. When drive signal generator 7 produces a reset signal R to gate terminal of second control MOS-FET 9, it is turned on to cause electric current to flow from control DC power source 10 through second resistor 14 and second control MOS-MET 9, thereby making low voltage at junction 37. Passed through second low pass filter 35 is a signal of low voltage level at junction 37 given to reset terminal R of RSF/F 31 which therefore is reset to cease output signal of high voltage level from output terminal Q to gate terminal of first MOS-FET 1 in order to turn it off. When the certain dead time has elapsed after the turning-off of first MOS-FET 1, second control circuit 50 produces a drive signal to gate terminal of second MOS-FET 2 to turn it on. Continuous repetition of the foregoing operations causes first and second MOS-FETs 1 and 2 to be alternately and iteratively turned on and off. Explanation is omitted regarding detailed methods for controlling pulse width and timing of output signals from second control circuit 50 and drive signal generator 7 and for setting dead time.
The foregoing half-bridge circuit would give rise to a rapid rise in reference voltage at junction 36 or 37 immediately after the turning-off of second MOS-FET 2 or turning-on of first MOS-FET 1 to thereby raise a large potential change dV/dt in high voltage side. At the moment, an electric current flows to electrically charge parasitic capacitances formed between drain and source terminals of first and second control MOS-FETs 8 and 9 while creating voltage drops across first and second resistors 13 and 14. Due to this, unlike under the normal operation, an abnormal signal might be fed to set or reset input terminal S or R of RSF/F 31 which therefore is led to a malfunction. In this connection, a proposal is made to the circuit of FIG. 6 that each anode terminal of first and second diodes 41 and 42 is connected between junction 6 of first and second MOS-FETs 1 and 2 and negative terminal of control DC power source 10; each cathode terminal of first and second diodes 41 and 42 is connected respectively to first and second control MOS-FETs 8 and 9. This proposal contemplates that parasitic capacitances or any negative potentials in first and second control MOS-FETs 8 and 9 are rapidly charged through first and second diodes 41 and 42 to control such negative potentials appeared in first and second series circuits 11 and 12 of first control circuit 5.
Upon occurrence of rapid potential rise dV/dt, voltage drops across first and second resistors 13 and 14 disadvantageously impede electric current flow to charge parasitic capacitances in first and second control MOS-FETs 8 and 9, and such insufficient charge in parasitic capacitances still causes malfunction of RSF/F 31. Meanwhile, noise may be produced due to the on-off operation of first and second MOS-FETs 1 and 2 or first and second control MOS-FETs 8 and 9, and exogenous noise may be superimposed on signals passing through first or second series circuit 11 or 12. To overcome such a trouble, the circuit shown in FIG. 6 comprises first and second low pass filters 34 and 35 connected respectively between junctions 36 and 37 and set and reset terminals S and R of RSF/F 31 to filter out by first and second low pass filters 34 and 35 noises of micro pulse width derived from unexpected voltage drop applied on first and second resistors 13 and 14 for prevention of malfunction in RSF/F 31. The following Patent Document 1 discloses a gate driver having a pulse filter for preventing a circuit malfunction at the time of occurrence of potential rise dV/dt.
However, the circuit shown in FIG. 6 is still disadvantageous because it needs first and second low pass filters 34, 35 of lower cutoff frequency to remove low frequency components of potential rise dV/dt. As well as contingent noises by potential rise dV/dt, first and second low pass filters 34, 35 removes high frequency components in regular signals through first and second control MOS-FETs 8 and 9, and therefore, drive signal generator 7 has to produce signals of widened pulse width. By way of example, if first and second control MOS-FETs 8 and 9 comprise constant current circuits for a few milliamperes, and input voltage Vin of 400 volts is applied from control DC power source 10 on first and second control MOS-FETs 8 and 9, first control circuit 5 incurs a great power loss during signal transmission because the main power loss is expressed by a formula: [(Vin+Vcc)*(a few milliamperes)*(pulse width)]. In this way, extension of pulse width obviously increases power loss, and may be in danger of inviting efficiency reduction in power control and damage or destroy of first control circuit 5.
On the other hand, in place of pulse filters, the following Patent Document 2 demonstrates a level shift circuit which comprises a first NOR circuit having a first input terminal connected between a first resistor and a first control switching element through two NOT circuits, and a second input terminal connected between a second resistor and a second switching element through another NOT circuit; and a second NOR circuit having a first input terminal connected between the first resistor and first control switching element through still another NOT circuit, and a second input terminal connected between the second resistor and second control switching element through further two NOT circuits. This level shift circuit utilizes voltage drops across first and second resistors to create regular and protective output signals from first and second resistors so that the protective signal from first resistor is used to inhibit an abnormal signal which may become a disturbing regular signal from second resistor, and adversely the protective signal from second resistor is used to inhibit an abnormal signal which may become a disturbing regular signal from first resistor.
[Patent Document 1] Japanese Patent No. 3,092,862 (FIG. 3)
[Patent Document 2] Japanese Patent Disclosure No. 2000-252809 (FIG. 1)